1. Field of the Invention
The present invention pertains to a method of forming a capacitor, in particular, a cup capacitor.
2. Brief Description of the Background Art
The implementation of digital information storage and retrieval is a common application of modern digital electronics. Memory size and access time serve as a measure of progress in computer technology. Quite often, storage capacitors are employed as memory array elements. As the state of the art has advanced, high density dynamic random access memory (DRAM) devices require smaller storage capacitors of the same capacitance by, for example, employing high dielectric constant materials or ferroelectric materials. The high dielectric constant materials or ferroelectric materials frequently include sintered metal oxide and may contain a substantial amount of reactive oxygen. In the formation of capacitors employing ferroelectric materials or films, the electrodes must be composed of materials which are difficult to oxidize, to prevent oxidation of the electrodes, which would decrease the capacitance of storage capacitors. Therefore, metals such as platinum, iridium, and ruthenium are preferred metals for use in the manufacture of capacitors for high density DRAMs. These metals are likely to be the preferred electrode materials in future generation memory devices. Platinum has emerged as a particularly attractive candidate because it is inert to oxidation and is known to have a leakage current ( less than 10xe2x88x929 amps/cm2) which is lower than that of many other metals. Platinum is also a good conductor.
As the state of the art has advanced, various designs for capacitor structures have emerged. One type of design is the cup capacitor, which is also known as a container capacitor or inlaid capacitor. Various cup capacitor designs and manufacturing techniques are described in the art. One method for forming conductive container structures on a supporting substrate of a semiconductor device includes the following steps: forming an insulating layer over parallel conductive lines and existing material on the surface of the supporting substrate; providing openings into the insulating layer, the openings forming vertical sidewalls in the insulating layer that resides between two neighboring conductive lines and thereby exposing an underlying conductive material; forming a sacrificial layer that makes contact with the underlying conductive material; forming a barrier layer overlying and conforming to the sacrificial layer; forming insulating spacers on the vertical sidewalls of the barrier layer; removing portions of the barrier layer and the sacrificial layer that span between the insulating spacers to thereby expose a portion of the underlying conductive material; removing the insulating spacers and thereby exposing the barrier layer; forming a conductive layer that conforms to the exposed barrier layer, makes contact to the underlying conductive material and forms multiple containers; forming a filler material in the container; removing portions of the conductive layer, the barrier layer and the sacrificial layer down to an upper portion of the insulating layer, thereby forming individual container structures; removing the insulating layer, thereby exposing the sacrificial layer surrounding the outer surfaces of the container structures; and removing the sacrificial layer, the remaining barrier layer and the fill layer, thereby exposing the outer and inner surfaces of the container structures.
According to another method for forming a stacked container capacitor, a first dielectric layer, a second dielectric layer, and a patterned mask layer are formed successively upon a semiconductor substrate. An anisotropic etch process is then performed to etch an aperture at least partially through the first dielectric layer using an anisotropic etch process. The second dielectric layer is then selectively etched relative to the first dielectric layer using an isotropic etch process, forming a ledge above the first dielectric layer and below the patterned masking layer. After removal of the masking layer, a first polysilicon layer, a third dielectric layer, and a second polysilicon layer are formed in the etched aperture. The filled aperture is then planarized until a flange of the first polysilicon layer formed into the ledge is exposed.
In a method of forming a container capacitor having a recessed conductive layer, which is typically made of polysilicon, chemical mechanical planarization is used to remove the layer of polysilicon and an overlying layer of photoresist from an upper surface of a substrate in which a container is formed. A wet etch is performed to selectively isolate a rim of the polysilicon within the container to recess the rim, while the remainder of the polysilicon in the container is protected by a photoresist layer.
In another method for forming a high-density DRAM cell with a polysilicon, cup-shaped capacitor, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed on the first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are then removed to define an opening. A second conductive layer is formed conformably on the substrate within the opening and on the first conductive layer. A sidewall structure is then formed within the opening on the sidewalls of the second conductive layer. Next, a portion of the second conductive layer which is not covered by the sidewall structure is removed. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer. A third conductive layer is formed conformably on the substrate to fill up the contact hole. Portions of the first conductive layer and the third conductive layer are removed to define a storage node. The second dielectric layer is then removed and a third dielectric layer is formed on the substrate. Finally, a fourth conductive layer is formed on the third dielectric layer to complete the formation of the capacitor.
A more detailed description of the Background Art described above can be found in U.S. Pat. No. 5,354,705, issued Oct. 11, 1994, to Mathews et al.; U.S. Pat. No. 5,627,094, issued May 6, 1997, to Chan et al.; U.S. Pat. No. 5,963,814, issued Oct. 5, 1999, to Walker et al.; and U.S. Pat. No. 6,090,663, issued Jul. 18, 2000, to Wu.
One prior art process for forming a cup capacitor is illustrated in FIGS. 3A through 3G. Referring to FIG. 3A, a starting structure 300 for forming a cup capacitor includes, from bottom to top, a semiconductor substrate 301, a dielectric layer 302 overlying the semiconductor substrate 301, and a patterned layer 304 of photoresist overlying the dielectric layer 302. Source 303 and drain 305 regions have been previously formed in semiconductor substrate 301 by ion implantation. Source 303 and drain 305 regions are connected by gate region 307. A polysilicon plug 306 and diffusion barrier layer 308 have been previously formed in dielectric layer 302, using conventional techniques known in the art. Polysilicon plug 306 contacts source region 303. Drain region 305 and gate region 307 are further connected to various interconnects (not shown).
Referring to FIG. 3B, dielectric layer 302 is pattern etched, using patterned photoresist layer 304 as a mask and etching techniques known in the art, to form a cup 310 in dielectric layer 302. Prior to performing further processing steps, the remaining photoresist layer 304 is removed, as shown in FIG. 3C.
Referring to FIG. 3D, a conformal conductive material layer 312 is then deposited over the sidewalls and bottom of the cup 310, using deposition techniques known in the art to provide a substantially conformal deposition. A layer 314 of a sacrificial material (typically silicon oxide) is then deposited to fill the cup 310, as shown in FIG. 3E.
Portions of the sacrificial material 314 overlying field surface 315 and cup 310 are then removed using a chemical-mechanical polishing (CMP) process (not shown). Conductive material 312 present on field surface 315 is also removed. However, CMP techniques have detrimental effects on the semiconductor structure, including substrate dishing, scratching, poor polishing uniformity across the substrate, and particulate residue, for example. As shown in FIG. 3F, the use of CMP planarization techniques can result in uneven surface topography 316 and loss of conductive material 312 near the edge of the cup 310. Following CMP planarization of the sacrificial material 314 and conductive material 312, the remaining sacrificial material is typically removed in a wet etch step, such as by immersion of the substrate wafer in an HF solution, to form the final structure 320 shown in FIG. 3G. Subsequent processing steps can then be performed to form a cup capacitor.
In addition to the problems encountered with the use of CMP planarization, the process described above is unattractive from a process integration standpoint. For example, following the formation of the structure shown in FIG. 3E, the substrate wafer must be moved to a different processing apparatus for chemical-mechanical polishing to planarize the sacrificial material 314 and to remove conductive material 312 from surface 315 adjacent cup 310. Then the substrate wafer must be moved to an HF bath to remove the remaining sacrificial material 314 within the cup 310, prior to the performance of subsequent plasma processing steps in a different apparatus to form the cup capacitor.
It would therefore be desirable to provide a method for forming a cup capacitor that is simple from a process integration standpoint and does not require the use of CMP and/or wet etch techniques.
Applicants have discovered a simple method for forming a cup capacitor. Applicants"" method typically involves only xe2x80x9cdryxe2x80x9d deposition and etching steps, and does not require the use of chemical-mechanical polishing. If desired, applicants"" method can be performed in a multi-chambered, dry processing apparatus, which permits easy control of the ambient which contacts surfaces of the capacitor during fabrication.
Accordingly, disclosed herein is a method of forming a cup capacitor comprising the following steps:
a) providing a semiconductor structure including a dielectric layer overlying a semiconductor substrate, wherein a cup is present in the dielectric layer, the cup having an opening at an upper surface of the dielectric layer;
b) depositing a conformal layer of a conductive material over the dielectric layer, including the sidewalls and bottom of the cup;
c) depositing a layer of a sacrificial material over the conductive material, in an amount sufficient to fill the cup;
d) removing sacrificial material present on an upper surface (field surface) of the conductive layer outside of and adjacent to the cup by plasma etching, using a plasma source gas which selectively etches the sacrificial material relative to the conductive material;
e) removing conductive material present on an upper surface (field surface) of the dielectric layer outside of and adjacent to the cup by plasma etching, using a plasma source gas which selectively etches the conductive material relative to the sacrificial material remaining inside of the cup; and
f) removing sacrificial layer material remaining inside of the cup by etching, using an etchant which selectively etches the sacrificial material inside of the cup relative to the conductive material inside of the cup.